1. Field of the invention:
The present invention relates to a multiplex transmission system of digital data and, more particularly, to a digital data multiplex control apparatus and a demultiplex control apparatus of multiplexed data.
2. Description of the Prior Art:
FIG. 32 is a diagram showing a frame format of a frame cons of twenty-four multiframes having a transmission rate of 1.544 Mbps shown in, e.g., the CCITT recommendation G. 704. In the diagram, reference numeral 1 denotes an F bit of one bit/frame and 2 indicates twenty-four data channels of TS.sub.1 to TS.sub.24 to which eight bits/frame are assigned and each of which has the capacity 64 kbps.
FIG. 33 is a diagram showing the content of the F bit 1 in FIG. 32 and shows a state in which a single loop of use is constructed by twenty-four multiframes.
FIG. 34 is a diagram showing a state in which asynchronous data of 1200 bps is multiplexed to the transmission frame shown in FIG. 32. In the diagram, reference numeral 3 denotes an asynchronous data signal of 1200 bps; 4 denotes a signal which is obtained by sampling the asynchronous data 3 of 1200 bps at many points by use of sync (synchronization) clocks of 9600 bps; and 5 denotes an envelope signal train in which the sampled signals 4 are combined every six bits and two bits consisting of an F' bit and an S' bit are added every six bits to thereby form one envelope, and its transmission rate is set at 12.8 kbps, which rate is 8/6 times faster than the 9600 bps of the sync clocks. Numeral 6 denotes a data train of the signal train of 64 kbps which is obtained by time sharingly multiplexing the envelope signal train 5 by the amount of five channels, and 7 indicates a transmission frame which is derived by inserting the signal train of 64 kbps into the TS (time slot) of 1.544 Mbps and multiplexing them.
The operation will now be described. In FIG. 32, the length of a transmission frame is 193 bits and is divided into the F bit 1 consisting of one bit and the 8-bit data channels 2 each consisting of twenty-four time slots.
Since the transmission rate is 1.544 Mbps, a transmission frame period is ##EQU1## Therefore, the capacity which is assigned to the F bit 1 is given by EQU F bit: one bit.times.8 kHz=8 kbps.
The capacity which is assigned to each TS 2 is obtained by EQU TS: eight bit.times.8 kHz=64 kbps.
Data are multiplexed at the basic rate of 64 kbps.
A method of using the F bit 1 will be described with reference to FIG. 33. The F bit 1 is divisionally used in a manner such that a frame sync pattern (FAS) which is inserted every four frames constructs one loop of "001011", a data link m of 4 kbps which is inserted every two frames constructs one an error check code (CRC-6) on a multiframe unit which is inserted every four frames constructs one loop of e.sub.1 to e.sub.6, and each loop is formed by twenty-four multiframes. Namely, the F bit having the capacity of 8 kbps is time sharingly used on a 24-multiframe unit basis. The capacity of 2 kbps is assigned to the frame sync pattern, the capacity of 4 kbps is assigned to the data link, and the capacity of 2 kbps is further assigned to the error check code (CRC-6).
An example in which the asynchronous signal 3 of 1200 bps is multiplexed to the transmission frame shown in FIG. 32 will now be explained with reference to FIG. 34. The 1200 bps signal 3 which is not synchronized with the transmission clocks is sampled by the clocks of 9600 bps which are synchronized with the transmission clocks and the data 4 of 9600 bps is derived. Next, the F' bit and S' bit each consisting of one bit are added every six bits of the 9600 bps data 4 and the rate is converted into the rate which is 8/6 times as high as the 9600 bps data 4, thereby producing the data train 5 of 12.8 kbps. Eight bits consisting of the F' and S' bits and six bits surrounded by the F' and S' bits in the 12.8 kbps data train 5 are called an envelope. Thereafter, the 12.8 kbps data train 5 is multiplexed to the 64 kbps train 6 by the amount of five channels. The multiplexed data train is multiplexed to one TS having the capacity of 64 kbps in the transmission frame 7 of 1.544 Mbps.
All of the signals of the other rates are also multiplexed at the basic rate of 64 kbps in a manner similar to the above.
Since the conventional data multiplex transmission system is constructed as mentioned above, data must be all multiplexed on a 64 kbps unit basis and it is necessary to match with the transmission frame rate by performing a complicated multiplexing procedure. In addition, the conventional system is not made in consideration of the substrate line of the transmission rate of 64 kbps.times.N (N=integer within a range of 1 to 24). If the system is applied to the subrate line by reducing the number of time slots which are used, there is a problem such that the data multiplex efficiency deteriorates or the like.
FIG. 35 shows an example of a construction of an apparatus on the transmission side when date is multiplexed as described above and shows transmitting sections of OIMUX and DOMUX extracted from "The New Data Transmission System", (2nd edition), pages 186 and 187, published by Sangyo Tosho Co., Ltd.
In the diagram, reference numeral 8 denotes a rate converting buffer to output data received from a terminal through an interface in accordance with a multiplex timing; 9 denotes a multiplex control section to multiplex the data of a plurality of channels which were stored in the rate converting buffers 8; 10 denotes a multiframe producing section to multiplex a multiframe pattern by the F' bit in the 64 kbps envelope train; 11 denotes an elastic buffer to temporarily store the multiplexed data and transmit synchronously with line clocks; and 12 denotes a frame sync pattern producing section to produce and add the F bit of the frame
The terminal data of the 1200 bps signal 3 which is not synchronized with the transmission line clocks is sampled by the 9600 bps clocks synchronized with the transmission line clocks and the sampled data are stored into the rate converting buffer 8.
Next, the 9600 bps signal 4 is read out in a burst manner from the rate converting buffer 8 by the control of the multiplex control section 9. The multiplex control section 9 outputs a gate signal having the width of six bits to each rate converting buffer 8. An F' bit and S' bit which were produced by the multiframe producing section 10, are added before and after the 6-bit data read out by the gate signal. In this case, these two bits are added in response to a multiframe multiplex timing signal which is generated from the multiplex control section 9. The rate of the 8-bit data train surrounded by the F' and S' bits including these F' and S' bits is converted into the rate which is 8/6 times as high as the original data train, thereby forming the data train 5 of 12.8 kbps. The data train 5 is called an envelope. This envelope is written as a continuous envelope train into the rate converting buffer 8 at the post stage and is multiplexed.
The subsequent multiplex control section 9 sequentially outputs the multiplex gate signal of five channels. In response to the gate signals, the data train 5 of 12.8 kbps is multiplexed by the amount of five channels to form the data train 6 of 64 kbps. The data train 6 is multiplexed to one TS 2 the transmission capacity of 64 kbps and written into the elastic buffer 11. On the other hand, the transmission data input to the elastic buffer 11 is processed so that its timing is matched with that of the transmission path. Thereafter, the F bit 1 as the frame sync bit is added to the delimiter of every transmission frame of 193 bits and the resultant transmission data are sent to transmission path. A bit pattern as a 20-multiframe pattern based on the CCITT recommendation X.50 is assigned to each F' bit in the data train 6 of 64 kbps.
The signals of other rates are also multiplexed into the transmission frame at the basic rate of 64 kbps in a manner similar to the above.
An example of a construction of the rate converting buffer 8 will now be described with reference to FIG. 36.
When a write gate signal is input to a write control section 8b, a write signal to write data into a FIFO (first-in first-out) memory 8a is output the data from each channel is stored into the FIFO memory 8a by an amount of a predetermined number of bits. At the same time, a storage amount detecting section 8d starts the counting-up operation to count the number of bits written in the FIFO memory 8a. When it is detected by the storage amount detecting section 8d that the data above a predetermined number of bits has been stored in the memory 8a, a multiplex gate signal whose timing is coincident with the multiplex timing is supplied to a read control section 8c. In response to this gate signal, the read control section 8c generates a read signal to the memory 8a, so that the multiplexed data are output to the next stage.
If the storage amount detecting section 8d detects that an amount of data stored in the memory 8a is less than a predetermined value, no read signal is output. Therefore, a process is performed in a manner such that a bit slip on the output side due to a long period jitter or the like of the processing clocks at the front stage hardly occurs.
The conventional multiplex apparatus is constructed as described above due to the relation with its data multiplex format and needs two kinds of multiplex processes at different processing timings. Two rate converting buffers to smooth the data which was multiplexed in a burst manner must be cascade connected and the like. Thus, the circuit scale increases. On the other hand, in order to match the rate of data series of 1200 bps.times.N series with that of data series of 64 kbps, an envelope is constructed. Therefore, the ratio of the data bits which actually occupy in the time slot is below 75% (6/8 time), so that there is a problem such that the multiplex efficiency deteriorates.
FIG. 37 shows an example of a construction of an apparatus for demultiplexing on the reception side the data multiplexed as described above and shows receiving sections of OIMUX and DOMUX extracted from "The New Data Transmission System", (2 nd edition), page 186 and 187, published by Sangyo Tosho Co., Ltd. In the diagram, reference numeral 13 denotes a frame sync detecting section to search the F bit 1 in the reception data train and to establish the frame synchronization; 14 denotes an elastic buffer to temporarily store the reception data and to match the timing with that for the demultiplex process at the post stage; 15 denotes a demultiplex control section to demultiplex the multiplexed data every plurality of channels; 16 denotes a rate converting buffer to output at a constant rate the data train which was demultiplexed in a burst manner; and 17 denotes a multiframe sync detecting section to establish the multiframe synchronization by the F' bit in the envelope train of 64 kbps.
FIG. 38 is a diagram showing an example of an internal construction of the rate converting buffer 16. In the diagram, reference numeral 16a denotes an FIFO (first-in first-out) memory which can asynchronousIy perform the writing and reading operations; 16b denotes a write control section to output a write signal to the FIFO memory 16a in response to a demultiplex gate signal; 16c denotes a read control section to supply a data reading timing signal to the FIFO memory 16a; and 16d denotes a storage amount detecting section to detect an amount of data stored in the memory 16a.
The F bit 1 is searched by the frame sync detecting section 13 from the reception data which was output from a line terminal apparatus (DCE, DSU, etc.). When a delimiter is detected every frame, a sync established signal is output to the demultiplex control section 15. On the other hand, the reception data input to the elastic buffer 14 is processed so as to match the timing with that for the demultiplex process and thereafter, it is output as the multiplexed data to the rate converting buffer 16. The demultiplex control section 15 sequentially generates the demultiplex gate signals for only the period of time corresponding to each time slot 2. Data are written from the elastic buffer 14 into the rate converting buffer 16 in a burst manner, respectively. However, data are output as a continuous envelope train of 64 kbps from the buffer 16 to the post stage. The envelope train of 64 kbps which is output from the buffer 16 is supplied to the multiframe sync detecting section 17. The multiframe synchronization of the 20-multiframe sequence is detected by the F' bit. When the multiframe sync established signal is output from the detecting section 17, the subsequent demultiplex control section 15 sequentially generates the demultiplex gate signals of five channels, thereby controlling the writing operation into the rate converting buffer 16 as the data for each terminal. Data are also written into the buffer 16 at the last stage in a burst manner similarly to the front stage. However, data are continuously output as the data of 9600 bps which is coincident with the terminal data rate. The demultiplex gate signal for the envelope train of 64 kbps is output from the demultiplex control section 15 or only the period of time corresponding to six bits excluding the F' and S' bits. The deletion of the F' and S' bits and the demultiplex are simultaneously performed.
An example of a construction of the rate converting buffer 16 will now be explained with reference to FIG. 38. When the demultiplex gate signal is input to the write control section 16b, a write signal to write data into the FIFO memory 16a is output and the multiplexed data are stored into the memory 16a by an amount of a predetermined number of bits. At the same time, the storage amount detecting section 16d starts the counting-up operation and counts the number of bits stored in the memory 16a. When the detecting section 16d determines that the data above a predetermined number of bits has been stored in the memory 16a, a read signal is supplied to the read control section 16c. In response to the read signal, the read control section 16c outputs the continuous read signals to the memory 16a at a constant speed, so that the demultiplexed data are output to the next stage. If the detecting section 16d detects that the amount of data stored in the memory 16a is less than a predetermined value, no read signal is output. This process is performed such that a bit slip on the output side due to the long period jitter or the like of the processing clocks at the front stage hardly occurs.
Since the conventional demultiplex control apparatus of multiplexed data are constructed as described above due to the relation with its data multiplex format, it is necessary to perform two kinds of demultiplexing processes at different processing timings. Two rate converting buffers to smooth the data which was demultiplexed in a burst manner also must be cascade connected. Thus, the circuit scale increases. In addition, since an envelope is constructed in order to match the rate of data series of 1200 bps x N with that of data series of 64 kbps, the ratio of the data bits which occupy the time slot to the total number of bits in the time slot is below 75% (6/8 time) and there is a problem such that the multiplex efficiency deteriorates.